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wireless components 2 band tv tuner mixer-oscillator-pll with balanced if-amplifier TUA6024 version 2.0 specification december 1999
edition 03.99 published by infineon technologies ag i. gr., sc, balanstra?e 73, 81541 mnchen ? infineon technologies ag i. gr. 13.01.00. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits im- plemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you ? get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? - 2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag. revision history: current version: 12.99 previous version:target data sheet page (in previous version) page (in current version) subjects (major changes since last revision) div div new layout
product info product info wireless components specification, december 1999 package TUA6024 product info general description the TUA6024 is a 5 v mixer/oscillator and sythesizer for analog and digital tv and vcr tuners. features general suitable for analog and digital ter- restrial tv tuner full esd protection mixer/oscillator high impedance mixer input for low/mid band low impedance mixer input for high band 4 pin oscillator for low/mid band 4 pin oscillator for high band if-amplifier balanced saw preamplifier low output impedance pll pll with short lock-in time high voltage vco tuning output fast i 2 c bus 3 npn bandswitch buffers internal low-mid/high switch lock-in flag power-down reset programmable reference divider ratios: 64, 80, 128 programmable charge pump cur- rent application ordering information type ordering code package TUA6024-k q67037-a1057 p-tssop-28-1 TUA6024-s q67037-a1056 p-tssop-28-1 the ic is suitable for pal tuner in tv- and vcr-sets or set-top receivers for analog tv and d igital v i deo b roadcasting.
1 - 1 wireless components specification, december 1999 1 table of contents 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 internal pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4 circuit description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 5 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 electrical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.1.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-4 bit allocation read / write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-5 description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-6 address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 table 5-7 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 table 5-8 reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3 i2c bus timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.4 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.1 gain (gv) test set-up in low/mid. . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.2 gain (gv) test set-up in high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.3 matching circuit for optimum noise figure in low/mid. . . . . . . . . . . 5-14 5.4.4 noise figure test set-up in low/mid . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.4.5 noise figure test set-up in high . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.4.6 measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
2 - 1 wireless components specification, december 1999 2 product description 2.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 contents of this chapter
product description 2 - 2 TUA6024 wireless components specification, december 1999 2.1 general description the TUA6024 device combines a digitally programmable phase locked loop (pll), with a mixer-oscillator block including two balanced mixers and oscilla- tors for use in tv and vcr tuners. the pll block with four selectable chip addresses forms a digitally programma- ble phase locked loop. with a 4 mhz quartz crystal, the pll permits precise set- ting of the frequency of the tuner oscillator up to 900 mhz in increments of 31.25, 50 or 62.5 khz. the tuning process is controlled by a microprocessor via an i 2 c bus. the device has three output ports. a flag is set when the loop is locked it can be read by the processor via the i 2 c bus. the mixer-oscillator block includes two balanced mixers (one mixer with high- impedance input and one mixer with a balanced low-impedance input), two fre- quency and amplitude-stable balanced oscillators for low/mid and high, an if amplifier, a low-noise reference voltage source, and a band switch. 2.2 features general suitable for analog and digital terrestrial tv tuner full esd protection mixer/oscillator high impedance mixer input for low/mid band low impedance mixer input for high band 4 pin oscillator for low/mid band 4 pin oscillator for high band if-amplifier balanced saw preamplifier low output impedance pll pll with short lock-in time high voltage vco tuning output fast i 2 c bus 3 npn bandswitch buffers internal low-mid/high switch lock-in flag power-down reset
product description 2 - 3 TUA6024 wireless components specification, december 1999 programmable reference divider ratios: 64, 80, 128 programmable charge pump current 2.3 application the ic is suitable for pal tuners in tv- and vcr-sets or set-top receivers for analog tv and d igital v i deo b roadcasting. 2.4 package outlines p-tssop-28-1
3 - 1 wireless components specification, december 1999 3 functional description 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 internal pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4 circuit description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.1 mixer-oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.2 pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.3 i2c-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 contents of this chapter
functional description 3 - 2 TUA6024 wireless components specification, december 1999 3.1 pin configuration pin_config figure 3-1 pin configuration vcc mixout sda highin highin low/midin mixout pllgnd scl as xtal phigh pmid plow oschighin oschighout oschighout oschighin osclow/midin osclow/midout rfgnd adc ifout ifout vt cp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TUA6024 osclow/midout osclow/midin
functional description 3 - 3 TUA6024 wireless components specification, december 1999 3.2 internal pin configuration table 3-1 pin definition and function pin no. symbol equivalent i/o-schematic average dc voltage low/mid high 1 oschighin 0.0 v 1.6 v 2 osc- highout 0.0 v 2.3 v 3 osc- highout 0.0 v 2.3 v 4 oschighin 0.0 v 1.6 v 5 osclow/ midin 1.6 v 0.0 v 6 osclow/ midout 2.8 v 0.0 v 7 osclow/ midout 2.8 v 0.0 v 8 osclow/ midin 1.6 v 0.0 v 2 1 3 4 5 6 8 7
functional description 3 - 4 TUA6024 wireless components specification, december 1999 table 3-1 pin definition and function (continued) pin no. symbol equivalent i/o-schematic average dc voltage low/mid high 9 rfgnd analog ground 0.0 v 0.0 v 10 adc v adc v adc 11 ifout 2.3 v 2.3 v 12 ifout 2.3 v 2.3 v 13 vt v t v t 14 cp 1.9 v 1.9 v 10 11 12 14 13
functional description 3 - 5 TUA6024 wireless components specification, december 1999 table 3-1 pin definition and function (continued) pin no. symbol equivalent i/o-schematic average dc voltage low/mid high 15 pmid 5 v or v ce 5 v 16 plow 5 v or v ce 5 v 17 phigh 5 v v ce 18 xtal 3.0 v 3.0 v 19 as v as v as 20 scl n.a. n.a. 15 16 17 18 19 20
functional description 3 - 6 TUA6024 wireless components specification, december 1999 table 3-1 pin definition and function (continued) pin no. symbol equivalent i/o-schematic average dc voltage low/mid high 21 sda n.a. n.a. 22 pllgnd digital ground 0.0 v 0.0 v 23 mixout 3.8 v 3.8 v 24 mixout 3.8 v 3.8 v 25 vcc supply voltage 5.0 v 5.0 v 26 low/midin 1.8 v 0.0 v 27 highin 0.0 v 0.9 v 28 highin 0.0 v 0.9 v 21 oscillator if amp. 24 23 26 27 28
functional description 3 - 7 TUA6024 wireless components specification, december 1999 3.3 block diagram block_diag figure 3-2 block diagram o s c l o w / m i d o u t o s c l o w / m i d o u t o s c l o w / m i d i n o s c h i g h o u t o s c h i g h i n o s c h i g h o u t o s c l o w / m i d i n o s c h i g h i n r f g n d a d c i f o u t i f o u t v t c p h i g h i n h i g h i n l o w / m i d i n v c c m i x o u t m i x o u t p l l g n d s d a s c l a s x t a l p h i g h p m i d p l o w mixer high mixer low/mid oscillator high oscillator low/mid saw driver prog. divider phase/ frequency comparator charge pump crystal oscillator reference divider ports i 2 c bus f div fl rf input high rf input low/mid lock detector f ref low or mid high low or mid high high low or mid 1234567891011121314 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc adc
functional description 3 - 8 TUA6024 wireless components specification, december 1999 3.4 circuit description 3.4.1 mixer-oscillator block the mixer oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for low and / or mid band and high, a refer- ence voltage source and a band switch. filters between tuner input and ic separate the tv frequency signals into two bands. the band switching in the tuner front-end is done by using two or three port outputs. in the selected band the signal passes a tuner input stage with mosfet amplifier, a double-tuned bandpass filter and is then fed to the bal- anced mixer input of the ic which has in case of low / mid a high-impedance input and in case of high a low-impedance input. the input signal is mixed there with the signal from the activated on chip oscillator to the if frequency which is filtered out at the balanced high-impedance output pair by means of a parallel tuned circuit. the following saw preamplifier has a low output imped- ance to drive the saw filter directly. 3.4.2 pll block the oscillator signal is internally dc-coupled as a differential signal to the pro- grammable divider inputs. the signal subsequently passes through a program- mable divider with ratio n = 256 through 32767 and is then compared in a digital frequency / phase detector to a reference frequency f ref = 31.25, 50 or 62.5 khz. this frequency is derived from a unbalanced, low-impedance 4 mhz crystal oscillator (pin xtal) divided by r = 128, 80 or 64. the phase detector has two outputs that drive two current sources of opposite palarity as charge pump. if the negative edge of the divided vco signal appears prior to the negative edge of the reference signal, the positive current source pulses for the duration of the phase difference. in the reverse case the i- current source pulses. if the two signals are in phase, the charge pump output (cp) goes into the high-impedance state (pll is locked). an active low-pass filter integrates the current pulses to generate the tuning voltage for the vco (inter- nal amplifier, external pullup resistor at tune and external rc circuitry). the charge pump output is also switched into the high-impedance state if the control bit t0 = 1. here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuity. tune may be switched off by the control bit os to allow external adjustments. if the vco is not oscillating the pll locks to a tuning voltage of 33v .
functional description 3 - 9 TUA6024 wireless components specification, december 1999 by means of control bit cp the pump current can be switched between two val- ues by software. this programmability permits alteration of the control response of the pll in the locked-in state. in this way different vco gains can be com- pensated, for example. the software-switched ports plow, pmid and phigh are general-purpose open-collector outputs. the test bit t1 = 1, switches the test signals f ref (i.e.f xtal / 64) and f div (divided input signal) to plow and pmid respectively. the lock detector resets the lock flag fl if the width of the charge pump current pulses is wider than the period of the crystal oscillator (i.e. 250 ns). hence, if fl = 1, the maximum deviation of the input frequency from the programmed fre- quency is given by ? f = i p (k vco / f xtal ) (c1+c2) / (c1c2) where i p is the charge pump current, k vco the vco gain, f xtal the crystal oscil- lator frequency and c1, c2 the capacitances in the loop filter ( see figure 4-1 evalu- ation board on page 2 ). as the charge pump pulses at i.e. 62.5 khz (= f ref ), it takes a maximum of 16 s for fl to be reset after the loop has lost lock state. once fl has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive f ref periods. therefore it takes between 128 and 144 s for fl to be set after the loop regains lock. 3.4.3 i 2 c-bus interface data is exchanged between the processor and the pll via the i 2 c bus. the clock is generated by the processor (input scl), while pin sda functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the i 2 c bus. the data from the processor pass through an i 2 c bus controller. depending on their function the data are subsequently stored in registers. if the bus is free, both lines will be in the marking state (sda, scl are high). each telegram begins with the start condition and ends with the stop condition. start condition: sda goes low, while scl remains high. stop condition: sda goes high while scl remains high. all further information transfer takes place during scl = low, and the data is forwarded to the control logic on the positive clock edge. the table ? bit allocation ? ( see table 5-4 bit allocation read / write on page 10 ) should be referred to the following description. all telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the sda line to low (acknowledge condition). the first byte is comprised of seven address bits. these are used by the processor to select the pll from several peripheral components (chip select). the lsb bit (r/w) determines whether data are written into (r/w = 0) or read from (r/w = 1) the pll.
functional description 3 - 10 TUA6024 wireless components specification, december 1999 in the data portion of the telegram during a write operation, the msb bit of the first or third data byte determines whether a divider ratio or control information is to follow. in each case the second byte of the same data type has to follow the first byte. if the address byte indicates a read operation, the pll generates an acknowl- edge and then shifts out the status byte onto the sda line. if the processor gen- erates an acknowledge, a further status byte is output; otherwise the data line is released to allow the processor to generate a stop condition. the status word consists the lock flag and the power-on flag. four different chip addresses can be set by appropriate dc level at pin as ( see table 5-6 address selection on page 11 ). while applying the supply voltage, a power-on reset circuit prevents the pll from setting the sda line to low, which would block the bus. the power-on reset flag por is set at power-on and when v cc falls below 3.2 v. it will be reset at the end of a read operation.
4 - 1 wireless components specification, november 1999 4 applications 4.1 circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 contents of this chapter
4 - 2 wireless components specification, november 1999 applications TUA6024 4.1 circuit application circuit.wmf figure 4-1 evaluation board 1p2 1p2 1p2 1p2 1p2 2p7 2p2 2p2 2p7 1k 33k l1 l2 l3 100p bb565 ba892 4n7 1k 3k3 100k 82p bb659c 2k7 2k7 4k7 4k7 1k 27p 2:10**) 1:1*) 2p2 22p 22p l4 68p 68p 47n 220 220 4n7 100p 18p 4n7 4n7 4n7 4n7 100p 100p 4n7 18p + 33 v 22k 4n7 22n 1n 4 mhz sda scl as phigh pmid plow adc high r gen = 75 ? low/ mid v cc 1n r load = 75 ? if output 100n 220 r gen = 75 ? 1234567891011121314 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TUA6024 c 1 c 2 table 4-1 recommended band limits in mhz rf input oscillator min max min max low 48.25 147.25 87.15 186.15 mid 154.25 423.25 193.15 462.25 high 432.25 855.25 471.25 894.25 table 4-1 coils turns wire l1 1.5 2 mm 0.4 mm l2 3.5 2.5 mm 0.5 mm l3 8.5 3 mm 0.5 mm l4 14.5 4 mm 0.3 mm *) toko b4f type 617db-1023 **) toko 7kl600 gcs-a1010dx
5 - 1 wireless components specification, december 1999 5 reference 5.1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.1.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-4 bit allocation read / write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-5 description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-6 address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 table 5-7 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 table 5-8 reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 table 5-9 a/d converter levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3 i2c bus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.4 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.1 gain (gv) test set-up in low/mid. . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.2 gain (gv) test set-up in high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.3 matching circuit for optimum noise figure in low/mid. . . . . . . . . . . 5-14 5.4.4 noise figure test set-up in low/mid . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.4.5 noise figure test set-up in high . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.4.6 measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 contents of this chapter
reference 5 - 2 TUA6024 wireless components specification, december 1999 5.1 electrical data 5.1.1 absolute maximum ratings warning the maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the ic may result. table 5-1 absolute maximum ratings, ambient temperature t amb =--20 c ... + 85 c parameter 1). symbol limit values unit remarks min max supply voltage v cc -0.3 6 v junction temperature t j +150 c storage temperature t stg -40 +125 c thermal resistance (junction to ambient) r thja 120 k/w pll cp v chgpmp -0.3 3 v i chgpmp 1 ma crystal oscillator pin xtal v xtal v cc v i xtal -5 ma bus input/output sda v sda -0.3 v cc v bus output current sda i sda(l) 5 ma open collector bus input scl v scl -0.3 v cc v chip address switch as v as -0.3 v cc v vco tuning output (loop filter) v t -0.3 35 v port outputs plow, pmid, phigh v p -0.3 v cc v i p(l) -1 25 ma t max = 0.1 sec. at 5.5 v total port output current i p(l) 40 ma t max = 0.1 sec. at 5.5 v mixer-oscillator mix inputs low/mid v mix v -0.3 3 v mix inputs high v mix u 2 v i mix u -5 6 ma
reference 5 - 3 TUA6024 wireless components specification, december 1999 table 5-1 absolute maximum ratings, ambient temperature t amb =--20 c ... + 85 c (continued) parameter 1) symbol limit values unit remarks min max vco base voltage v b -0.3 3 v vco collector voltage v c v cc v esd-protection 2). all pins v esd 1 kv 1). all values are referred to ground (pin), unless stated otherwise. currents with a positive sign flows into the pin and currents with a negative sign flows out of pin. 2). according to mil std 883d, method 3015.7 and eos/esd assn. standards5.1 - 1993
reference 5 - 4 TUA6024 wireless components specification, december 1999 5.1.2 operating range within the operational range the ic operates as described in the circuit description. the ac / dc characteristic limits are not guaranteed. table 5-2 operating range parameter symbol limit values unit test conditions l item min max supply voltage v cc +4.5 +5.5 v programmable divider factor n256 32767 low/mid mixer input frequency range f mixv 30 500 mhz high mixer input frequency range f mixu 400 900 mhz low/mid oscillator frequency range f oh 65 560 mhz high oscillator frequency range f ou 430 950 mhz ambient temperature t amb -20 +85 c
reference 5 - 5 TUA6024 wireless components specification, december 1999 5.1.3 ac/dc characteristics ac / dc characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. typical characteristics are the median of the production. table 5-3 ac/dc characteristics with t a 25 c, v cc symbol limit values unit test conditions litem min typ max supply supply voltage v cc 4.5 55.5 v current consumption i cc 56 70 84 ma digital unit pll crystal oscillator connections xtal crystal frequency f xtal 3.2 4.0 4.8 mhz series resonance crystal resistance r xtal 10 100 ? series resonance oscillation frequency f xtal 3,99975 4,000 4,00025 mhz f xtal = 4 mhz input impedance z xtal -500 -700 -900 ? f xtal = 4 mhz charge pump output cp high output current i cph 90 220 300 a cp = 1, v cp = 2 v low output current i cpl 22 50 75 a cp = 0, v cp = 2 v tristate current i cpz +1 na t0 = 1, v cp = 2 v output voltage v cp 1.0 2.5 v pll locked drive output vt (open collector) high output current i th 10 a v th = 33 v, t0 = 1 low output voltage v tl 0.4 vi tl = 1.0 ma i 2 c-bus bus inputs scl, sda high input voltage v ih 3 5.5 v low input voltage v il 0 1.5 v high input current i ih 10 a v ih = v s low input current i il -10 a v il = 0 v bus output sda (open collector) high output current i oh 10 a v oh = 5.5 v low output voltage v ol 0.4 vi ol = 3 ma
reference 5 - 6 TUA6024 wireless components specification, december 1999 table 5-3 ac/dc characteristics with t a 25 c, v cc (continued) symbol limit values unit test conditions litem min typ max edge speed scl,sda rise time t r 300 ns fall time t f 300 ns clock timing scl frequency f scl 0 400 khz high pulse width t h 0.6 s low pulse width t l 1.3 s start condition set-up time t susta 0.6 s hold time t hsta 0.6 s stop condition set up time t susto 0.6 s bus free t buf 1.3 s data transfer set-up time t sudat 0.1 s hold time t hdat 0 s input hysteresis scl, sda v hys 200 mv pulse width of spikes which are suppressed t sp 0 50 ns capacitive load for each bus line c l 400 pf port outputs plow, pmid, phigh (open collector) high output current i poh 1 a v poh = 5 v low output voltage v pol 0.5 vi pol = 25 ma adc port input high input current i adch 10 a low input current i adcl -10 a address selection input as high input current i ash 50 a v ash = 5 v low input current i asl -50 a v asl = 0 v
reference 5 - 7 TUA6024 wireless components specification, december 1999 table 5-3 ac/dc characteristics with t a 25 c, v cc (continued) symbol limit values unit test conditions litem min typ max analog unit low/mid band section (including if amplifier) voltage gain g v 20 23 26 db f rf = 43.25 to 463.25 mhz, f if = 33.4 to 58.75 mhz mixer noise figure nf 911 db f rf = 43.25 to 463.25 mhz mixer input impedance r i 1 23 k ? serial equivalent cir- cuit, f mixv = 100 mhz c i 23 pf serial equivalent cir- cuit, f mixv = 100 mhz oscillator frequency shift, pll unlocked ? f osc(v) 400 khz v cc = 5 v 10% oscillator frequency drift, pll unlocked ? f osc(t) 500 khz ? t = 25 c oscillator frequency drift, pll unlocked ? f osc(t) 100 khz t = 5 s up to 15 min after switching on
reference 5 - 8 TUA6024 wireless components specification, december 1999 table 5-3 ac/dc characteristics with t a 25 c, v cc (continued) symbol limit values unit test conditions litem min typ max oscillator pulling, pll unlocked v i 100 108 dbv ? f = 10 khz f rf = 48.25 mhz v i 100 108 dbv ? f = 10 khz f rf = 399.25 mhz n + 5 pulling, pll unlocked n+5 -50 dbc f rf = 48.25 mhz, f rf1 = 83.25 mhz, p rf =p rf1 = 80dbv n+5 -50 dbc f rf = 399.25 mhz, f rf1 = 439.25 mhz, p rf =p rf1 = 80dbv oscillator phase noise 1). osc -80 -86 dbc/hz fm = 10khz if suppression a if 15 20 db v mixb = 80 dbv high band section (including if amplifier) voltage gain g mixu 31 34 37 db f rf = 367.25 mhz to 863.25 mhz, f if = 33.4mhz to 58.75 mhz mixer noise figure nf mixu 69 db f rf = 367.25 to 615.25 mhz 710 db f rf = 623.25 to 863.25 mhz mixer input impedance r i 14 20 26 ? serial equivalent cir- cuit, f mixu = 600 mhz l i 6 10 14 nh serial equivalent cir- cuit, f mixu = 600 mhz
reference 5 - 9 TUA6024 wireless components specification, december 1999 table 5-3 ac/dc characteristics with t a 25 c, v cc (continued) symbol limit values unit test conditions litem min typ max oscillator frequency shift, pll unlocked ? f osc(v) 400 khz v cc = 5 v 10% oscillator frequency drift, pll unlocked ? f osc(t) 800 khz ? t = 25 c oscillator frequency drift, pll unlocked ? f osc(t) 100 khz t = 5 s up to 15 min after switching on oscillator pulling, pll unlocked v mixu 100 108 dbv ? f = 10 khz f rf = 375.25 mhz 100 108 dbv ? f = 10 khz f rf = 847.25 mhz n + 5 pulling, pll unlocked v mixu -50 dbc f rf = 471.25 mhz, f rf1 = 511.25 mhz, p rf =p rf1 = 80dbv v mixu -50 dbc f rf = 847.25 mhz, f rf1 = 887.25 mhz, p rf =p rf1 = 80 dbv oscillator phase noise 1) -80 -86 dbc/hz fm = 10khz if suppression a if 15 20 db v mixb = 80 dbv saw preamplifier if output impedance r if 80 ? serial equivalent circuit, f if = 38.9 mhz l if 7 nh rejection at the if outputs divider interference rejection 2) a70 dbc p rf = 80 dbv channel s02 beat rejection 2). a66 dbc f rf = 76.25 mhz p rf = 80 dbv this value is only guaranteed in lab. 1). measured in evaluation board. 2). channel s02 beat is the interfering product of f rf , f if and f osc of channel s02, f beat = 37.35 mhz. the possible mechanisms are f osc - 2 x f if or 2 x f rfpix - f osc . measured in evaluation board.
reference 5 - 10 TUA6024 wireless components specification, december 1999 5.2 programming table 5-4 bit allocation read / write byte msb bit6 bit5 bit4 bit3 bit2 bit1 lsb ack remark s write data address byte 11 00 0ma1 ma0 0 a progr. divider byte 1 0n14 n13 n12 n11 n10 n9 n8 a progr. divider byte 2 n7 n6 n5 n4 n3 n2 n1 n0 a control byte 1cp t1 t0 fp rsa rsb os a bandswitch byte xx xx xp- high pmid 1). plow 1.) a tua 6024-k bandswitch byte xx xx p- high x pmid 1.) plow 1.) a tua 6024-s read data address byte 11 00 0ma1 ma0 1 a status byte por fl xx xx xx a 1). in a tuner plow and pmid are interchangeable. both bits switch the ic into low/mid (vhf) mode. table 5-5 description of symbols symbol description ma0, ma1 address selection bits ( see table 5-6 address selection on page 11 ) n14 to n0 programmable divider bits: n = 2 14 x n14 + 2 13 x n13 + ..... + 2 3 x n3 + 2 2 x n2 + 2 1 x n1 + n0 cp charge pump current: bit = 0: charge pump current = 50 a bit = 1: charge pump current = 220a t1, t0 test bits ( see table 5-7 test modes on page 11 ) fp reserved for future purposes, actually ignored, default: 1 rsa, rsb reference divider bits ( see table 5-8 reference divider ratio on page 11 ) os tuning amplifier control bit: bit = 0: enable v t bit = 1: disable v t plow, pmid, phigh npn ports control bits: bit = 0: npn open-collector output is inactive bit = 1: npn open-collector output is active fl pll lock flag bit = 1: loop is locked por power-on reset flag flag is set at power-on and reset at the end of read operation x don ? t care
reference 5 - 11 TUA6024 wireless components specification, december 1999 table 5-6 address selection voltage at as ma1 ma0 (0...0.1) * v cc 00 open circuit 01 (0.4...0.6) * v cc 10 (0.9...1) * v cc 11 table 5-7 test modes test mode t1 t0 normal operation 00 charge pump output, cp is in high-impedance state 01 plow = f div output, pmid = f ref output 10 not used 11 table 5-8 reference divider ratio reference divider ratio f ref 1). rsa rsb 80 50 khz x 0 128 31.25 khz 0 1 64 62.5 khz 1 1 1). with a 4 mhz quartz. table 5-9 a/d converter levels voltage at adc a2 a1 a0 (0...0.15)*v cc 00 0 (0.15...0.3)*v cc 00 1 (0.3...0.45)*v cc 01 0 (0.45...0.6)*v cc 01 1 (0.6...1)*v cc 10 0
reference 5 - 12 TUA6024 wireless components specification, december 1999 5.3 i 2 c bus timing diagram telegram examples: start-adb-db1-db2-cb-bb-stop start-adb-cb-bb-db1-db2-stop start-adb-cb-ab-db1-db2-stop start-adb-db1-db2-stop start-adb-cb-bb-stop abbreviations: start= start condition adb= address byte db1= prog. divider byte 1 db2= prog. divider byte 2 cb= control byte bb= bandswitch byte stop= stop condition note: sda: scl: ack. ack. 2nd byte 1st byte 3rd byte ack. ack. ack. addressing ma r/w ma 4th byte
reference 5 - 13 TUA6024 wireless components specification, december 1999 5.4 test circuits 5.4.1 gain (g v ) test set-up in low/mid gvhf2 z i >> 50 ? => v i = 2 x v meas = 80 dbv v i = v meas + 6db = 80 dbv v 0 = v ? meas + 16 db (transformer ratio n1:n2 and transformer loss) g v = 20 log(v 0 / v i ) 5.4.2 gain (g v ) test set-up in high guhf2 v i = v meas = 70 dbv v 0 = v ? meas + 16 db (transformer ratio n1:n2 and transformer loss) g v = 20 log(v 0 / v i ) + 1 db (1 db = insertion loss of balun) 50 ? spectrum analyser device under test ifout low/ midin ifout v' meas v 0 v i 50 ? c transformer n1 : n2 = 10 : 2 turns n1 n2 50 ? v v meas rms votmeter 50 ? spectrum analyser device under test ifout highin ifout v' meas v 0 v i 50 ? c transformer n1 : n2 = 10 : 2 turns n1 n2 50 ? v v meas rms votmeter balun 1:1 highin
reference 5 - 14 TUA6024 wireless components specification, december 1999 5.4.3 matching circuit for optimum noise figure in low/mid nfm 5.4.4 noise figure test set-up in low/mid nfvhf2 22p 22p 7 turns wire 0.5 mm coil 5.5 mm 1n in out 15p 22p 1n 50 semi rigid cable 300 mm long 96 pf/m 33db/100m in out for f rf = 150 mhz loss = 1.3 db image suppression = 13 db for f rf = 50 mhz loss = 0 db image suppression = 16 db device under test ifout low/ midin ifout c transformer n1 : n2 = 10 : 2 turns n1 n2 noise figure meter noise source nf = nfmeas - loss of matching circuit (db) matching circuit in out
reference 5 - 15 TUA6024 wireless components specification, december 1999 5.4.5 noise figure test set-up in high nfuhf2 5.4.6 measurement of f ref and f div freq_meas_cof device under test ifout highin ifout c transformer n1 : n2 = 10 : 2 turns n1 n2 highin balun 1:1 noise source noise figure meter loss of balun = 1 db nf = nfmeas - loss of balun (db) 5k 5k 18p device under test v vcc counter counter + 5 v 4 mhz pmid plow test mode: t1 = 1, t0 = 0 f q = f ref * r r: reference divider ratio f vco = f div * n n: divider ratio f ref f div

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